1. Field of the Invention
The invention generally relates to interface systems for interfacing a computer system host to an asynchronous transfer mode (ATM) system and in particular to partitioning load and unload functions for use with segmentation and reassembly of packets and cells within such an interface system.
2. Description of the Related Art
ATM technology is emerging as the preferred technology for implementing broadband integrated services data networks ISDNs (B-ISDN). A B-ISDN is a system for interconnecting computer systems, local area networks (LANs), telephones, facsimiles, etc., to facilitate communication of data, voice and video between the systems. B-ISDN typically employs fiber optics as a communication medium. An ATM system facilitates the transmission of data over the B-ISDN by defining a set of "data connections" where each connection represents a virtual circuit having a particular source and destination and an associated data transmission.
Data provided by a computer system, LAN, telephone, etc., may initially be stored in packets of data. ATM-based systems, however, transmit and process cells of data. Accordingly, a method or apparatus must be provided for converting packets into cells (segmentation) and for converting cells into packets (reassembly). Both segmentation and reassembly are two-step processes. For segmentation, packets are received from the host system and stored in memory (load), then converted to cells and output to the ATM system (unload). For reassembly, cells are received from the ATM system, assembled into packets and stored in memory (load), then extracted from memory and output to the host bus (unload).
Conventionally, an application specific integrated circuit (ASIC) segmentation and reassembly (SAR) chip is provided which performs the aforementioned segmentation and reassembly processes. The conventional SAR chip, however, does not separate the load and unload steps, either functionally, logically or physically. In other words, load and unload components are integrated together.
Certain disadvantages, however, occur as a result of the integration of load and unload components. Load components must account for any constraints imposed by the host, but need not be constrained by ATM-specific requirements. Likewise, unload components are subject to limitations imposed by the ATM, but are unaffected by any limitations of the host. Therefore, any modification to the host need only affect the load components and any modification to the ATM system need only affect the unload components. Yet, when load and unload components are integrated as in conventional SAR chips, a modification to either the host or the ATM system may require a complete re-design of the SAR chip. Moreover, the integration of load and unload components can prevent the exploitation of circuitry optimized for use only with the host or only with the ATM system.
It would be desirable, therefore, to provide an improved ATM system interface shown as a SAR chip which avoids the disadvantages arising in systems providing integrated load and unload components. Aspects of the present invention are drawn to such an improved system. In particular, it is an objective of the invention to partition the load and unload components of the segmentation process and also to partition the load and unload functions of the reassembly process.
Any attempt to partition the load and unload components, however, must provide for adequate communication between the partitioned components to allow efficient throughput of data. Such is particularly problematic within ATM system interfaces configured to accommodate the transmission of data on a plurality of data connections each potentially operating at different data transmission rates. For example, if an external buffer memory is employed to facilitate the overall transfer of cells, a partitioned load component may need to repeatedly poll queues within the external buffer memory that correspond to different transmission rates to determine when additional cells should be loaded therein. Accordingly, another objective of the invention is to provide an efficient technique for allowing partitioned load and unload components to communicate with each other to provide for efficient throughput of data while also eliminating the need for polling if an external buffer memory is used.